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严韫洲, 喻文健, 裴春艳, 胡超. 面向集成电路互连电容提取的三维交互显示程序设计与实现[J]. 计算机辅助设计与图形学学报, 2022, 34(4): 507-514. DOI: 10.3724/SP.J.1089.2022.19442
引用本文: 严韫洲, 喻文健, 裴春艳, 胡超. 面向集成电路互连电容提取的三维交互显示程序设计与实现[J]. 计算机辅助设计与图形学学报, 2022, 34(4): 507-514. DOI: 10.3724/SP.J.1089.2022.19442
Yan Yunzhou, Yu Wenjian, Pei Chunyan, Hu Chao. A 3D Interactive Visualization Program for Interconnect Capacitance Extraction of Integrated Circuits[J]. Journal of Computer-Aided Design & Computer Graphics, 2022, 34(4): 507-514. DOI: 10.3724/SP.J.1089.2022.19442
Citation: Yan Yunzhou, Yu Wenjian, Pei Chunyan, Hu Chao. A 3D Interactive Visualization Program for Interconnect Capacitance Extraction of Integrated Circuits[J]. Journal of Computer-Aided Design & Computer Graphics, 2022, 34(4): 507-514. DOI: 10.3724/SP.J.1089.2022.19442

面向集成电路互连电容提取的三维交互显示程序设计与实现

A 3D Interactive Visualization Program for Interconnect Capacitance Extraction of Integrated Circuits

  • 摘要: 为了辅助电容提取程序包RWCap的开发和调试,并增强三维结构数据Cap3D文件的可视性,开发了三维交互显示程序RWCapView,直观、清晰地展示Cap3D文件描述的导体空间结构.首先读入Cap3D文件,利用ANTLR辅助生成的LL语法分析器解析出三维坐标数据;再利用深度缓冲算法和扫描线算法进行图像的输出,并同步显示导体空间坐标轴和标尺以标识其方位和尺寸;通过实现基础仿射变换支持对导体空间的多角度细致观察,建立导体和金属层、介质层的关联,支持多种导体筛选方式.基于实际版图的实验结果表明,该程序解析并输出10 000块以上导体的设计版图总耗时3 s左右,进行各种变换的响应时间约100 ms,可以快速处理导体数量很大的大规模集成电路设计版图.

     

    Abstract: In order to assist the development and debugging of the RWCap program package, and increase the visuality of Cap3D files, a three-dimensional(3D) interactive visualization program RWCapView is developed to show intuitively and clearly the special structure illustrated by the Cap3D files. The program reads in Cap3D files and extract 3D coordinate data from it using a LL grammar parser generated by ANTLR. Then Z-buffering algorithm and sweep line algorithm are utilized to output the image, together with the axes and scale of the conductor space to identify its position and measurement. By implementing basic affine transformation detailed multi-angle inspection of the conductor space is supported. And by constructing linkages among metal layers, medium layers and conductors, multiple ways of filtering conductors are supported. Experiments based on real life layouts show that it takes about 3 seconds in total to parse and output the image of a layout with more than 10 000 conductor blocks, with about 100 milliseconds response time when performing various transformation or filtering, proving that it can efficiently handle very large scale integrated(VLSI) circuit layouts.

     

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