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任向隆, 田泽, 张骏, 郑新建, 韩立敏, 王治, 张亮, 李哲, 许宏杰, 刘航, 张宏伟. 面向OpenGL 2.0的图形处理器图像处理单元体系结构[J]. 计算机辅助设计与图形学学报, 2019, 31(10): 1858-1870. DOI: 10.3724/SP.J.1089.2019.17646
引用本文: 任向隆, 田泽, 张骏, 郑新建, 韩立敏, 王治, 张亮, 李哲, 许宏杰, 刘航, 张宏伟. 面向OpenGL 2.0的图形处理器图像处理单元体系结构[J]. 计算机辅助设计与图形学学报, 2019, 31(10): 1858-1870. DOI: 10.3724/SP.J.1089.2019.17646
Ren Xianglong, Tian Ze, Zhang Jun, Zheng Xinjian, Han Limin, Wang Zhi, Zhang Liang, Li Zhe, Xu Hongjie, Liu Hang, Zhang Hongwei. An Architecture of Image Processing Unit for OpenGL 2.0 Oriented GPU[J]. Journal of Computer-Aided Design & Computer Graphics, 2019, 31(10): 1858-1870. DOI: 10.3724/SP.J.1089.2019.17646
Citation: Ren Xianglong, Tian Ze, Zhang Jun, Zheng Xinjian, Han Limin, Wang Zhi, Zhang Liang, Li Zhe, Xu Hongjie, Liu Hang, Zhang Hongwei. An Architecture of Image Processing Unit for OpenGL 2.0 Oriented GPU[J]. Journal of Computer-Aided Design & Computer Graphics, 2019, 31(10): 1858-1870. DOI: 10.3724/SP.J.1089.2019.17646

面向OpenGL 2.0的图形处理器图像处理单元体系结构

An Architecture of Image Processing Unit for OpenGL 2.0 Oriented GPU

  • 摘要: 为实现图形处理器的自主可控,设计了面向OpenGL2.0图形处理器图像处理单元的体系结构.首先,确定了图像处理单元的单元结构及工作流程;其次,针对每条所处理的函数设计了数据通路;随后,依据各函数的数据通路和OpenGL规范,整理了各模块的处理函数对照表;最后,实现了其体系结构,并在虚拟仿真和FPGA平台进行了纹理加载/获取、卷积、颜色表、柱状图等功能验证,对纹理加载进行了峰值性能验证,面向FPGA和ASIC进行了代价评估.结果表明,该结构能够实现图像处理单元所规定的系列功能,性能满足设计要求,峰值情况每秒可处理30帧2K×2K图像,实现代价可接受.目前,该图像处理单元已集成到完全自主研发的图形处理器之中.

     

    Abstract: The architecture of image processing unit towards OpenGL 2.0 was designed for autonomy and controllability of graphics processing unit. Firstly, the structure and workflow of image processing unit were determined. Secondly, for each function being processed, a data path was designed for it. Then, functions each module need processing were concluded according to the data path of each function and the OpenGL specification. Finally, the architecture is implemented, and functions such as texture loading/acquisition, convolution, color table and histogram were validated both on virtual simulation platform and FPGA platform. Moreover, the peak performance of texture loading was validated, and the costs of texture loading were evaluated both for FPGA and ASIC. The results show that the structure can realize the series of functions specified by the image processing unit, and the performance meets the design requirements. In peak condition, 30 frames of 2 K?2 K images can be processed within a second, and the implementation cost is acceptable. Currently, the image processing unit has been integrated into a fully self-developed graphics processor.

     

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