一个简单的65nm MOSFET失配模型
A Simplified 65nm MOSFET Mismatch Model
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摘要: MOSFET的精确匹配对模拟和混合集成电路的性能至关重要,随着器件特征尺寸减小至纳米,将MOSFET失配模型进行改良以适应新工艺显得十分迫切.文中应用改进的ALPHA律平均漏电流模型拟合65 nm器件的HSPICE仿真数据,并提取了相关工艺参数,该模型与BSIM4模型数据相比平均相对误差为1.70%,相对标准差8.26%;再利用该模型并结合偏差传递公式实现了一个简单的65 nm工艺MOS器件电流失配标准差计算模型.实验结果显示,该模型与HSPICE蒙特-卡罗仿真数据相比平均相对误差为7.69%,相对标准差为10.49%.这表明文中模型简单、有效,又能保证精度.Abstract: Mismatch models to fit new process have become particularly urgent with MOS devices feature size are scaled to nanometer scale due to the importance of MOSFET exact match for the final performance of analog and mixed ICs.This paper utilizes an improved alpha-power-law to fit 65nm MOS model data and extract related process parameters.In comparison with BSIM4 model data, the relative average error and standard deviation is 1.70% and 8.26 respectively, then a simplified 65 nm MOSFET mismatch model for calculating standard deviation is presented based on this improved model and POV expression.The experimental results show that the relative average error and standard deviation is 7.69% and 10.49% respectively between this mismatch model and Monte-Carlo simulation data, this indicates that the proposed 65nm mismatch model is simple, effective, and accurate.