Abstract: Due to the high computing and memory requirements of the global automated image registration algorithm,an accelerator called BWAGIR II is proposed.It adopts a dedicated two-rank-multi-bank memory to support accessing 16 pixels within a 4×4 interpolating window in one cycle.And some logics are designed to support hybrid operations between a fixed-point operand and a floating-point operand directly.Experimental results from a FPGA-based implementation show that a throughput of over 258×10⁶ pixels/s is achieved with 5 BWAGIR II units.