Abstract: Traditional technology mapping algorithms don't break hierarchical boundary between specific-purpose blocks and LUTs for heterogeneous FPGA,thereby the solution space of mapping could be decreased to some extent.This paper proposes an efficient technology mapping algorithm by utilizing a regional regrouping approach to break hierarchical boundary between those heterogeneous blocks.It first adopts greedy heuristics for general mapping through giving priority to specific-purpose blocks with good performance,and then takes advantage of self-defined signed-cones to implement regional regroup among sub-netlists.Benefiting from regrouping strategy,it not only breaks the hierarchical boundary between specific-purpose blocks and LUT,and also reduces the cost of area and delay.Experimental results show this algorithm can reduce area of logic blocks by 12.2% and decrease circuit delay by 2.5% on average,compared to acknowledged Berkeley ABC mapping algorithm.