Abstract: Based on the analysis of functional fault models of dual-port word-oriented SRAM and CAM used in embedded caches, efficient DS-March CE test algorithm and DC-March CE test algorithm aiming at embedded applications have been presented. These new algorithms are a good tradeoff between fault coverage rates and test periods in solving the problems of inefficient tests that happen in testing embedded caches when the previous algorithms were directly applied. Using March CE algorithms and taking the characters of cache circuit into account, a centralized BIST test scheme is designed and implemented. With overhead area less than 2%, this scheme is able to simultaneously detect the faults of the memories with various capacities and port categories, as well as the special structure of TLB.