Abstract: For the problem of cells defect-tolerant mapping in defect existed CMOL circuits, this paper proposes a defect-tolerant mapping method based on gate node interval selection. The logic circuit is topologically sorted to calculate the gate logic level, then interval gate nodes with defective connects are punished to improve the selected probability to be reallocated. The experiment results indicated that compared with the published algorithms, the proposed method shows that 30.68% of CPU runtime is reduced traded with 0.18% increase of wire length when the struck-open defect rate of nano-devices is up to 40%.