Abstract: Soft error caused by transient faults can become an important issue for chip failures under deep sub-micron manufacturing process.This paper proposes a soft-error-tolerant BIST structure,i.e.,FT-CBILBO.As an evolution of CBILBO,FT-CBILBO reuses MISR to construct DMR fault-tolerant scheme to reduce the overhead.FT-CBILBO can block soft error by inserting code word state preserving element to tolerant SEU-induced soft error.The experimental results under UMC 0.18μm process show that area overhead of FT-CBILBO ranges from 28.37% to 33.29%,and performance overhead ranges from 4.99% to 18.20%.