Abstract: In order to improve the accuracy of parasitic extraction and timing analysis of integrated circuits(ICs),and perform the capacitance extraction with three-dimensional(3D) field solver,a fast transformation method is proposed to convert IC layout data.The method reads in GDSII file and vertical technology information,and then determines whether conductor blocks are connected or overlapped based on a sweep line algorithm.After that,the data structures of list and union-find set are used to describe the interconnect blocks and the connectivity among them,which is necessary for the subsequent capacitance extraction and timing analysis.Finally,the method outputs the 3D structure data for capacitance extraction field solver.The experimental results based on actual layouts show that,the proposed method is 4X~7X faster than the method based on pairwise analysis,and the speedup ratio increases as the number of blocks in the design increases.The time complexity of the proposed method is O(nlog n),where n is the number of blocks in the design layout.Therefore,the method is able to handle actual circuit layout with more than 10,000 blocks efficiently.