Abstract: In order to reduce the storage requirements for the test patterns,a vertical and horizontal test data compression BIST scheme based on the test pattern generation of twisted-ring counter is proposed．Firstly,the test pattern width is compressed with the input reduction technique．Secondly, an efficient seed selection algorithm targeting the minimization of the selected seed volumes for the test set embedding case is utilized to compress the test set into the seed set．Experimental results on the ISCAS 89 benchmark circuits show that the proposed scheme requires 44％ less test storage,79％ less test patterns,and 41％ less hardware overhead compared with the previous scheme．