Abstract: To shorten the test time of 3D through silicon via (TSV) , a design for testing TSVs is proposed.The memory die and the logic die are compatible with JESD 229 and IEEE 1149.1standard, respectively.Firstly, a module for controlling boundary scan chains on the memory die is added to the logic die.Then, by transforming the boundary scan chains on the logic die, two connection modes, serial and parallel, are implemented.Finally, extra registers are added in the logic die to store TSV testing configuration bits.Experimental results show that, 0.4% area overhead is induced to the IEEE 1149.1 boundary scan circuit, and TSV test time is reduced by 6X in comparison with the previous work.