Abstract: To improve circuit debuggability and reduce logic resource usage, this paper proposes an approach for scan chain insertion in hardware emulation platform, which exploits partially used look-up tables（LUTs） on FPGAs to realize the extra logic required by the scan chain. The approach firstly finds all partially used LUTs which are connected to the inputs of D flip-flops in a netlist. Secondly, the contents of the found LUTs are changed to accommodate the extra logic, in order to convert the D flip-flops to scan flip-flops. Finally, all scan flip-flops are connected to form the scan chain. The whole approach is automated and can be easily integrated into the current FPGA development flows. The experimental results on ITC’99 benchmark circuits show that the proposed approach can effectively reduce logic resource usage by 22.9% on average.