Abstract: For the hardware implementation of fast Fourier transform(FFT) processor in orthogonal frequency division multiplexing(OFDM) based communication system,this paper proposes an efficient and reconfigurable VLSI architecture.Based on the memory-based architecture,a dual-path pipelined shared-memory FFT architecture and an elaborately designed control scheme are proposed which can provide high computation efficiency with less chip area.Furthermore,a reconfigurable pipelined butterfly unit is also designed for multi-mode calculation.A test chip based on the architecture has been designed and applied to DVB-T/H system.Synthesis and layout are carried out by SMIC 0.18 μm standard CMOS process and its hardware scale and power dissipation is 56 k logic gate and 33.5 mW@20 MHz,respectively.Compared with known VLSI architecture for FFT,the proposed design reduces area and power dissipation efficiently.