Abstract: Polygon Boolean operations in integrated circuit layouts are fundamental to critical processes such as De-sign Rule Checking and Optical Proximity Correction in Electronic Design Automation (EDA). As semi-conductor technology scales down to 5 nm and below, the efficiency of Boolean operations on ul-tra-large-scale layouts has become a core bottleneck constraining the layout sign-off flow. To address the limited parallelism of existing algorithms when processing massive polygons, this paper proposes a poly-gon Boolean operation method based on an improved Greiner-Hormann (GH) algorithm. This method adopts the degenerate intersection classification rules of Foster’s algorithm as the basis for topological re-construction. Furthermore, it designs a dual-level uniform grid and an intersection-insertion decoupled da-ta organization architecture tailored for large-scale Layer-to-Layer scenarios, enabling efficient filtering and parallel processing of candidate edge pairs. On this basis, a CPU-GPU collaborative execution frame-work is constructed, which offloads the compute-intensive intersection operations to the GPU while retain-ing topological reconstruction on the CPU. Experimental results demonstrate that, while ensuring topolog-ical correctness, the single-threaded CPU implementation of the proposed method outperforms mainstream tools such as KLayout and Clipper2. The GPU-accelerated version achieves a speedup of over 2× in ul-tra-large-scale layout scenarios, while also accommodating the processing demands for complex polygons in fields such as GIS. The proposed dual-level uniform grid and intersection-insertion decoupled architec-ture enhances the parallel scalability and execution efficiency of the GH algorithm in large-scale Lay-er-to-Layer polygon set scenarios, holding significant theoretical research value and engineering applica-tion prospects for advancing the optimization of EDA layout sign-off flows.