Reversible Circuit Synthesis Method by Combining Factoring and Boolean Expression Diagram
1) (School of Electrical, Electronic and Computer Science, Guangxi University of Science and Technology, Liuzhou 545006)2) (School of Electronics and Information Engineering, Jinggangshan University, Ji’an 343009)
In order to reduce the cost of the resulting circuits, a reversible circuit synthesis method by combining factoring and Boolean expression diagram (BED) is proposed. For a given cover representing the exclu-sive-sum-of-products (ESOP) expansion of a Boolean function, cubes in the ESOP expansion represented by shared zero-suppressed multiple-output decision diagrams are first factored by leveraging algebraic division, then a BED is built from the factored ESOP cover and a reversible circuit is synthesized from the BED by mapping a BED node to a cascade of reversible gates. The proposed synthesis method is evaluated using benchmark func-tions. Experimental results show that the proposed synthesis method is time efficient. Compared to the existing reversible circuit synthesis methods using a directed acyclic graph as the representation model for Boolean func-tions, the proposed synthesis method can reduce the quantum cost and the number of qubits of the resulting re-versible circuits in many cases. On average, compared to the synthesis method by combining variables grouping and BED, the proposed synthesis method can reduce the quantum cost and the number of qubits by 5.01% and 5.47%, respectively.