Double Node Upset Tolerant Latch Based on Hybrid TMR
Huang Zhengfeng1), Feng Zhicheng1), Yao Huijie1), Yi Maoxiang1), Ouyang Yiming2), and Liang Huaguo1)*
1) (School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei 230009)2) (School of Computer & Information, Hefei University of Technology, Hefei 230009)
With the continuous development of technology, internal nodes of integrated circuits are more sensitive to high energy particle striking, and radiation induced soft error in latch increases quickly. Research shows that double node upset caused by charge sharing is becoming a serious reliability issue under 90nm technology. This paper presented two hardening latches: TMR-2D1R latch and TMR-1D2R latch, which are based on hybrid TMR mechanism. Traditional TMR latch comprises three D-latches and one voter.TMR-2D1R latch comprises two D-latches, one RHM and one voter. TMR-2D1R can partially tolerate single event double node upset. TMR-1D2R latch comprises one D-latch, two RHMs and one voter. TMR-1D2R latch can totally tolerate single event double node upset. Compared with other hardening latches, the proposed latch make better tradeoff in terms of delay, power consumption, area and hardening performance.