Zhao Sisi, Xia Yinshui*, Zhang Junli, and Li Qiongying
(Institute of Circuits and System, Ningbo University, Ningbo 315211)
To overcome the limitation based on single traditional Boolean (TB) logic optimization of logic function, the area optimization method based on TB logic and Reed-Muller (RM) logic called dual logic with graph representation is proposed. Firstly, logic function is represented in called AXIG (AND/XOR/INV Graph) based on the operator set of AND, XOR, INV and dual logic graph representation of logic function is obtained. Then, the obtained AXIG is partitioned into two parts with suitable for TB logic and RM logic implementation, respectively. Finally, the area optimization of logic function is implemented. Experimental results show that the proposed method is more efficient than published logic synthesis method.
Reed-Muller logic; AND-XOR-inverter graph; partition; area optimization