Integrated Circuit Test Data Compression Scheme Built-in Generalized Folding Technology
Zhan Wenfa, Wu Qiong, Cheng Yifei, and Wu Haifeng
(School of Computer & Information, Anqing Normal University, Anqing 246133)
Due to the automatic test equipment in the process of chip need to transmit a large number of test data to the tested chip, resulting in wasting a lot of test data transmission time, an integrated circuit test data compression scheme based on generalized folding technology is proposed. First, construct a directed graph, complete test set are mapped to the directed graph; Second, the complete test set is divided into several generalized folding set by find the longest paths; Finally, store the generalized folding set seeds and generalized folding distance. In addition, the decompression structure of generalized folding set is proposed. In theory, the storage of the whole test set can be the storage of some generalized folding seeds and distance. Experimental results on part of the ISCAS89 benchmark circuits show that, under the same experimental conditions the compression effect is better than that of Golomb coding, FDR coding, EFDR coding and the fold set mature compression method.
built-in self-test; folding set; test data compression; built-off self-test; coding