Low Power Latch Design for Single Event Upset Tolerance
Liang Huaguo1), Li Xin1), Wang Zhi2), and Huang Zhengfeng1)*
1) (School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei 230009)2) (Hefei Core Storage Electonic Limited, Hefei 230000)
As CMOS technology scaling down in the nanometer region, latch circuits are becoming more sensitive to soft errors induced by energetic particles in space radiation environment. To mitigate the effects of soft errors on the latch circuits, a single event upset (SEU) resilient and low cost hardened latch design is proposed in 45 nm CMOS technology. The proposed latch utilizes three C-elements to form an interlocked structure in which the output state of each C-element is determined by the output of the other two C-elements; when the output node of any C-element is affected by an SEU, the proposed latch will bring the affected node back to the correct state through interlocked feedback paths; no node exhibits a high impedance state after the transient faults die down, thus the proposed latch is suitable for a low power circuit with clock gating. Extensive SPICE simulation results demonstrate that the proposed latch provides a better tradeoff among delay, power, area and soft error tolerance and saves 57.53% area-power-delay-product on average in comparison with previous latches; detailed Monte Carlo simulation results indicate that the proposed latch features less sensitive to process, temperature and voltage variations.
single event upset; soft errors; C-element; transient fault; self-recovery